Evolving the Real-time Graphics Pipeline for Micropolygon Rendering a Dissertation Submitted to the Department of Computer Science and the Committee on Graduate Studies of Stanford University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy

The modern real-time graphics pipeline is a versatile parallel architecture that accommodates a wide range of rendering techniques. The architecture is implemented by heavily optimized graphics processors (GPUs) that employ a mixture of applicationprogrammable and fixed-function processing resources, yet its design lends itself to a simple programming model easily understood by non-expert programmers. A major goal of future graphics systems is rendering geometrically complex, filmquality scenes in real time. Unfortunately, current GPU implementations not only require additional compute capability to handle high-resolution surfaces represented by subpixel-area micropolygons, the fundamental graphics pipeline operations of surface tessellation, rasterization, and shading execute inefficiently under this advanced workload. This dissertation evolves the graphics pipeline architecture and its associated rendering algorithms to increase system efficiency when processing micropolygons. The proposed redesign extends the pipeline with a new parallel algorithm for high-quality, adaptive surface tessellation, making it possible to generate crack-free meshes that represent surfaces accurately, but without excessive numbers of micropolygons. It increases rasterization throughput using micropolygon-parallel processing and analyzes the cost of rasterizer support for motion blur and camera defocus. It also adds pipeline logic to detect and avoid redundant shading computations, reducing shading costs more than eight times. The resulting real-time micropolygon rendering pipeline architecture increases rendering efficiency and, due to its evolutionary nature, maintains the graphics pipeline’s simple programming model and the throughput-optimized design of a GPU’s programmable processing cores.